Byte-addressable non-volatile memory (NVM) technologies, such as memristor, provide persistent data storage that can be accessed directly through processor load and store instructions. Processors can employ fast on-chip caches to hide the latency to access the NVM, which may reorder updates to NVM and complicate the implementation of crash-consistency protocols. In this case, augmenting write-back caches with ordering mechanisms or explicitly flushing cache lines can be used to ensure crash-consistency.